1. Field of the Invention
The present invention relates to a floating point addition and subtraction arithmetic circuit. More particularly, it relates to a floating point addition and subtraction arithmetic circuit capable of performing preprocessing in addition or subtraction operations rapidly, which comprises a circuit for detecting a sticky bit.
2. Description of the Related Art
In order to perform the floating point arithmetic rapidly, various means have been proposed in the arithmetic techniques using a computer. To speed up the arithmetic operation, for example, carry transfer time accompanied by the rounding is reduced in this kind of technique. As another example, an effective high speed arithmetic operation can be realized by speeding up the timing for creating a sticky bit. A sticky bit means the logical OR of bits shifted out by right-shifting the mantissa of the smaller exponent number of two numerals represented by the floating point number in order to conform the exponent parts with each other.
As one example of the prior art of reducing the carry transfer time accompanied by the rounding, and which is not a directly related art, "Floating Point Arithmetic System" is disclosed in Japanese Patent Publication Laid-Open No. 3-171228. Herein, disclosed is a floating point arithmetic system including a mantissa creating means for aligning mantissas of operands to be processed and creating two sets of operand mantissas from the mantissa and the reverse mantissa, a rounding judging means for determining the necessity of the increment in the respective roundings when assuming that the normalization of the arithmetic solution is necessary and assuming that it is not necessary, a first adding means for calculating a first solution including the rounding when assuming that the normalization of the arithmetic solution is not necessary, a second adding means for calculating a second solution including the rounding when assuming that the normalization of the arithmetic solution is not necessary, a selecting means for selecting a true solution from the first and second solutions, and a normalizing means for normalizing the selected true solution to obtain the arithmetic result of the solution in the operand mantissa, and the system in which the judgment of the rounding is performed in each case depending on the necessity of the normalization of the arithmetic solution prior to the arithmetic operation of the mantissa, and according to the judgment result, the arithmetic operation and the rounding operation in the mantissa are simultaneously performed, so to reduce the carry transfer times in the arithmetic process, thereby realizing a high speed addition or subtraction operation.
In the conventional floating point addition and subtraction arithmetic circuit, a sticky bit is detected as follows. First of all, the exponent parts of input operands are compared with each other. The mantissa of the operand having the smaller exponent part is shifted to the right (on the side of the least significant bit) by the difference of the exponent parts so as to align the smaller exponent part at the larger exponent part. All the bits shifted out from the mantissa are ORed.
A circuit for detecting a sticky bit as mentioned above, for example, has the structure as FIG. 3, accompanied by an arithmetic circuit for aligning the operands to be processed by digit. In FIG. 3, a comparison subtraction circuit 110 makes a comparison between the respective exponent parts of the first and second operands, and subtracts the smaller exponent part from the larger one of the first and second operands, so to provide a comparison signal 111 and a shift amount signal 112. For example, when the exponent part of the first operand is larger, the exponent part of the second operand is subtracted from the exponent part of the first operand and the subtraction result is supplied to a shift circuit 130 as the shift amount signal 112.
A mantissa selecting circuit 120 selectively delivers the mantissa of input operand on the basis of the comparison signal 111. The circuit 120 sends the mantissa of the input operand having the larger exponent part to an absolute value addition and subtraction arithmetic circuit 160, and sends the mantissa of the input operand having the smaller exponent part to the shift circuit 130. In the above example, the mantissa of the first operand is sent to the absolute value addition and subtraction arithmetic circuit 160 and the mantissa of the second operand is sent to the shift circuit 130.
The shift circuit 130 shifts the mantissa received from the mantissa selecting circuit 120 to the right according to the shift amount signal 112, so as to align the operand by digit. The shift circuit 130 delivers the shift result to the absolute value addition and subtraction arithmetic circuit 160, and supplies all the bits that are shifted out from the mantissa part after the operand is right-shifted, to an OR circuit 140. In the above example, the mantissa of the second operand is shifted to the right according to the shift amount signal 112. All the bits shifted out of the bit width of the mantissa on the right side are delivered to the OR circuit 140.
The OR circuit 140 estimates the logical OR of all the bits shifted out, received from the shift circuit 130, thereby to detect the sticky bit, and supplies it to the absolute value addition and subtraction arithmetic circuit 160.
The absolute value addition and subtraction arithmetic circuit 160 performs the absolute value addition or subtraction operation on the mantissa directly received from the mantissa selecting circuit 120, the mantissa having been aligned which is received from the shift circuit 130, and the sticky bit received from the OR circuit 140.
As set forth hereinabove, in the conventional floating point addition and subtraction arithmetic circuit, sticky bit detection is realized by estimating the logical OR of the bits overflown after the operand is right-shifted. Therefore, it takes a lot of time in the preprocessing before starting the addition or subtraction operation, which results in disadvantageously decreasing the efficiency.